This module should fit into a Verilog system as if it was a CMOS/CCD
sensor chip and the JPEG image is what the sensor captured.  The
Verilog portion of this module essentially takes care of the clocks,
horiziontal, vertical syncs and scaning location and all other typical
sensor driving functions.  Currently, this module only supports
emulation of 8-bit mono sensors.  If the input image is RGB or other
color format, the module will use OpenCV routines to convert it to
8-bit grayscale.  However, if the image is an 8-bit bayer pattern
image, (such as what a color sensor would produce), then it will work
correctly as a bayer pattern sensor (it would just push the pixels in
the same order as the image file).

The given Verilog file "sensor.v" is generic in nature, It provides
many normal ports, however, most are not driven or do anything when
driven.  It would be easy to modify this file to better match your
real sensor specs.  See code below for module instanciation:

defparam   i_ccd.source = "image.jpg";
module	sensor (MCLK,	// Master clock
		MRST,	// Master Reset - active low
		ARO,	// Array read Out.
		ARST,	// Array Reset. Active low
		OE,	// output enable active low
		SCL,	// I2C clock
		SDA,	// I2C data
		OFST,	// I2C address ofset
		D,	// data output
		DCLK,	// Data output clock
		BPF,	// Black Pixel Flag
		HACT,	// Horizontal Active
		VACT);  // Vertical Activ

parameter source = "image.jpg";

To get the basic functionallity, the instanciating module should
provide MCLK, which will be the same frequency as the pixel clock, and
set the parameter "source". The sensor module will then drive the
VACT (frame sync), HACT (line sync) and D (8-bit pixel data) with the
apprpate values and timing for the image size.  Once started, the
module will continusly stream the same image file for every frame.
The sample instaciation is shown below:

   defparam   i_ccd.source = "image.jpg";
   sensor i_ccd(.MCLK(DCLK),    // Master clock
		.MRST(MRST),    // Master Reset - active low
		.ARO(ARO),      // Array read Out.
		.ARST(ARST),    // Array Reset. Active low
		.OE(1'b0),      // output enable active low
		.SCL(SCL0),     // I2C clock
		.SDA(SDA0),     // I2C data
		.OFST(1'b1),    // I2C address ofset
		.D(PXD[7:0]),   // data output
		.DCLK(),        // Data output clock
		.BPF(BPF),      // Black Pixel Flag
		.HACT(HACT),    // Horizontal Active
		.VACT(VACT)     // Vertical Active
		);


To load and use an image, the Verilog module will use two system
tasks, $cv_open() and $cv_pixel().  The $cv_open() task will load an
image file into memory and return the width, height and depth of the
read image.  The $cv_pixel() call will return exactly one 8-bit pixel
value from a specified (x,y) location.  The sample "sensor.v" has the
counters to keep v-sync and h-sync


The $cv_open() task takes three arguments:
$cv_open(sourceFile, numCols, numRows, numChannels); 

sourceFile: (input) The path to the image file, it's a string type
parameter it can be specified as a verilog 'parameter' or in the
system task itself.

numCols:  (output) A 16-bit register value with the number of columns in the
image (width of the image in pixels).

numRows:  (output) A 16-bit register value with the nunber of rows in
the image (height of the image in pixels).

numChannels:  (output) 8-bit register value.  Currently only returns the value '1' for grayscale